Field programmable gate arrays (FPGAs) are advanced chips developed from PAL, GAL, CPLD and other programmable chips. Current FPGAs are mostly based on look-up table techniques and are composed essentially of programmable input/output blocks (IOBs), programmable logic blocks (CLBs), programmable interconnections (PIs), configuration SRAMs, block RAMs and digital delay phase-locked loops (DLLs) and etc. Testing an FPGA involves structural analysis of resources possibly present therein, configuring the FPGA into a circuit with a specific function through test configuration, test stream implementation and other processes, and then testing the circuit at an application level for completing the testing of its functional and performance parameters.
In general terms, complete testing of the internal resources of an FPGA involves designing a variety of configuration patterns for the different testing resources, downloading them to the FPGA at multiple times, repeated application of stimuli and collection of test responses, as well as fault testing through analysis of the responses. Therefore, for an FPGA test method, how to speed up each configuration process to reduce the configuration time overhead in the testing and how to automate repeated configuration and testing to allow the fast online FPGA configuration to be combined with fast testing are critical.
Current automatic test equipment (ATE) in the IC field is designed and manufactured to be suitable for the testing of most ICs. However, FPGA testing is exceptional since it is impossible to test the internal resources of an FPGA unless the resources have been configured to allow the FPGA has an internal circuitry that meets the design or application requirements prior to the testing of its functional and performance parameters. ATE-enabled configuration in a test step generally involves generating ATE-executable test stimuli (test vectors) through modifying configuration data manually or by means of a PC program. However, when the configuration data are voluminous, for example, those for an FPGA chip using a bumping process with a large number of pins that is more than one thousand, the aforementioned conversion process will be very complex and suffer from a lack of ease of use and etc., which would make it incapable of efficient use in FPGA chip testing. Thus, in order to meet such configuration and test requirements, there is a need to develop FPGA test and configuration solutions for advanced test equipment-based testing of FPGA chips, in particular, those using a bumping process.
Currently, there are a number of methods available for FPGA configuration, including boundary-scan configuration, SPI/BPI configuration dedicatedly used by Xilinx, Inc., system ACE configuration and direct loading of configuration vectors by the system. However, the boundary-scan approach is suitable mainly for online configuration and commissioning, and the method dedicatedly used by Xilinx, Inc. allows the storage of only one section of configuration code at a time and is not suited to repeated configuration and testing. Additionally, the system ACE configuration method requires a dedicated control chip and CF card for system ACE control, making it cumbersome to be used, need increased system setup cost, take up larger space and inapplicable to scenarios with more configuration files.